In today's competitive situation, it is quite risky to make complex electronic devices rich in embedded software available to the market faster, but at the same time ensure that they are cheaper and more reliable. Untested hardware designs inevitably lead to rework, increase design costs and extend the delivery time of the netlist for the layout process, and ultimately delay the time-to-market goal, with devastating effects on revenue sources.
Postponing the testing of embedded software also has the potential to miss out on the opportunity to go public, with more serious consequences.
Because of this, the verification of the project cycle greatly occupies planning time becomes a very common thing. The underlying reason is that tracking and eliminating errors is extremely difficult, especially if the software content of a system-on-a-chip (SoC) grows at a rate of about 200% per year. In contrast, the hardware portion of the design grew by only about 50%.
While virtual prototyping and field-programmable gate array (FPGA) prototypes have received attention in early embedded software testing, they do not contribute to software and hardware integration. The former lacks the hardware accuracy required to track hardware errors, and the latter has limited capabilities for hardware debugging required to eliminate errors as quickly as possible.
As a result, development teams and project managers have turned to hardware simulation as the basis for their validation strategies. Hardware emulation is a versatile verification tool with many advantages, including hardware and software co-verification or testing hardware and software integration. It has been noticed by software developers because it is the only verification tool that ensures that embedded system software works properly with the underlying hardware. This is also worth noting for hardware engineers working on debugging complex SoC designs because engineers can use this method to track software errors in hardware or hardware errors in software behavior. Other benefits of hardware emulation include fast assembly capabilities, software verification, comprehensive design debugging, and scalability to meet the design of billions of application-specific integrated circuit (ASIC) gates. In addition, it can handle billions of verification cycles at a high rate necessary to validate embedded software and perform system verification (Figure 1).
In the past, hardware debugging and testing was the only work in the project cycle validation section, which was managed by hardware software simulation driven by the Hardware Description Language (HDL) testbench. Traditional large box hardware simulations are only used for the largest designs. Many development teams have used formal validation to complement software simulation to increase base coverage and ensure that no special use cases are missed. However, only hardware emulation can complete all verification tasks for SoC design in a more feasible time and mitigate operational issues associated with event-based software emulation.
SoC's software content makes co-verification a very important part of the verification strategy because it confirms that the hardware and software parts of an embedded SoC are validated and interacted correctly before the filming.
In the past, if hardware problems occurred after designing a slice, software developers had to try to code around the problem as much as they could. By verifying the software before the SoC is completed, the design team can resolve hardware issues before entering the silicon stage. As mentioned earlier, hardware emulation checks are used to ensure that embedded software runs on hardware according to specifications.
In the past, various debugging engines were used for software debugging. Each engine has a core that takes full advantage of the hardware's visibility and control of the internal workings of the processor. Although some debugging features are provided, the ability to diagnose problems is limited due to the access methods provided by the processor. In addition, since traditional software debugging usually occurs in real systems, software developers execute the actual code on actual hardware at the target system speed. This way they can quickly find the wrong program with a lot of code.
These traditional techniques are not effective when debugging SoCs because there is no real hardware to execute code at real system speeds. In general, hardware can be simulated as long as the code is executed and the software simulator provides all hardware visibility. But the problem is speed - debugging code is a slow way.
For example, if the SoC is designed to run programs on Linux, software developers must complete Linux boot in billions of clock cycles before the software can begin execution. It is roughly estimated that this will take more than 28 years to complete the Linux boot at a typical software simulation speed of about 10 Hz.
Regardless of debugging hardware or software, traditional hardware and software debugging tools are not aware of any of the other situations. If you are using a complex large SoC design, it is inefficient to try to find both types of debugging independently when trying to find a problem.
The combination of the two is the most ideal method, so hardware simulation can save time. SoC hardware is typically implemented in an FPGA or other programmable device and is faster. In this setup, depending on the speed of operation, Linux boot can be completed in as little as 15 minutes. Hardware emulation provides breakpoint and waveform control and visibility similar to hardware debuggers.
Confirm that the SoC design works as expectedHardware simulation stands out from the crowd with its high performance, which is an increasingly important requirement driven by software requirements. It confirms that the SoC design works as planned and is suitable for handling complex designs with up to one billion ASIC equivalent gates and can complete more than one trillion verification cycles per month. Even so, the use of hardware emulation for thorough and detailed functional verification is still the most cost-effective and efficient way to debug (Figure 2).
Introducing transaction-level modeling (TLM) and transaction processor availability transforms hardware simulation into a series of vertical market virtual platform test environments. As part of a validation intellectual property (IP) combination, a transaction processor is a high-level abstraction model of peripheral functions or protocols. Transaction processors are typically provided as off-the-shelf IP and can be used in a variety of different protocols. Typical transaction processors typically include PCIe, USB, FireWire, Ethernet, Digital Video, RGB, HDMI, I2C, UART, and JTAG devices.
Better verify more complex systemsPreviously, hardware design was independent of the development of software to be executed on the chip. But today, as the number of SoC processors doubles and each generation contains twice as much software content, software issues are a priority for development teams and project managers. Now, the development team has confirmed that the SoC is considered complete after the software is expected to work properly on the hardware platform.
The SoC is a comprehensive embedded system that requires hardware emulation to verify that it works. Through hardware simulation, the development team can plan more strategically and implement debugging methods based on multiple abstractions. They can track errors between hardware and embedded software to determine the problem. In a more cost-effective and efficient way, they save time in the process and significantly reduce the risk of missing the opportunity to go public.
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